Configurable array logic realisation of a bit level systolic array for IIR filters

The first order IIR filter can be defined by y_n=b₁y_n-1+ u_n where u_n=a₀ x_n+a₁x_n-1 where x_n is the nth sample of the data stream, and a₀, a₁, and b₁ are the filter coefficients. The paper is centred on the efficient CAL implementation of the multiplier/adder and other cells computing the recursive term. It is shown that CAL provides an ideal implementation of the IIR filter since the CALs can be dynamically reconfigured to implement particular filter coefficients, a₀, a₁, and b₁ . Packages such as the OrCAD Schematic Design Tools can be used to capture the schematic for the IIR filter