Title :
Configurable array logic realisation of a bit level systolic array for IIR filters
Author_Institution :
Algotronix Ltd., Edinburgh, UK
Abstract :
The first order IIR filter can be defined by yn=b1yn-1+ un where un=a0 xn+a1xn-1 where xn is the nth sample of the data stream, and a0, a1, and b1 are the filter coefficients. The paper is centred on the efficient CAL implementation of the multiplier/adder and other cells computing the recursive term. It is shown that CAL provides an ideal implementation of the IIR filter since the CALs can be dynamically reconfigured to implement particular filter coefficients, a0, a1, and b1 . Packages such as the OrCAD Schematic Design Tools can be used to capture the schematic for the IIR filter
Keywords :
digital filters; logic CAD; logic arrays; CAL; CAL implementation; IIR filters; OrCAD Schematic Design Tools; bit level systolic array; configurable array logic; multiplier/adder; recursive term; schematic;
Conference_Titel :
User-Configurable Logic - Technology and Applications, IEE Colloquium on
Conference_Location :
London