CMOS TSPC latch circuits for pass-transistor logic

In this work, latch circuits are presented for the design of true single phase clocked (TSPC) pass-transistor (PT) networks. The latches consist of N-clocked and P-clocked sections, which can be used in conjunction with NMOS pass-transistor networks to implement general logic functions. In each N or P section, the signal to be latched is input to a positive feedback regenerative circuit, which restores the incomplete logic-level at the output of the latch. The latch sections rely on the circuit topology to minimize power dissipation resulting from reduced input signal swing, rather than on transistor threshold adjustments or special well or substrate biasing. Thus, it is possible to realize pass-transistor circuits with reduced power dissipation in ordinary CMOS processes