0.12μm P-MOSFETs with High-K and Metal Gate Fabricated in a Si Process Line on 200mm GeOI Wafers

Author

Royer, C. Le ; Clavelier, L. ; Tabone, C. ; Deguet, C. ; Sanchez, L. ; Hartmann, J.-M. ; Roure, M.-C. ; Grampeix, H. ; Deleonibus, S.

Author_Institution

CEA-LETI, Grenoble

fYear

2007

fDate

11-13 Sept. 2007

Firstpage

458

Lastpage

461

Abstract

Abstract-For the first time, we report on deep sub-micron (gate length down to 0.12 mum) GeOI pMOSFETs. The Ge layer obtained by hetero-epitaxy on Si wafers has been transferred using the Smart-Cuttrade process to fabricate 200 mm GeOI wafers with Ge thickness down to 60 nm. A full CMOS compatible p-MOSFET process was implemented with HfO₂/TiN gate stack. The electrical characterization of the fabricated devices and the systematic analysis of the measured performances (I_ON I_OFF Gm, S, DIBL) demonstrate the potential of pMOSFET on GeOI for advanced technological nodes.

Keywords

MOS integrated circuits; MOSFET; Ge; P-MOSFET; Smart-Cut process; gate stack; heteroepitaxy; metal gate fabrication; systematic analysis; CMOS process; CMOS technology; Chemical vapor deposition; Hafnium oxide; High K dielectric materials; High-K gate dielectrics; MOSFET circuits; Performance analysis; Substrates; Tin;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid State Device Research Conference, 2007. ESSDERC 2007. 37th European

Conference_Location

Munich

ISSN

1930-8876

Print_ISBN

978-1-4244-1123-8

Electronic_ISBN

1930-8876

Type

conf

DOI

10.1109/ESSDERC.2007.4430977

Filename

4430977