Title :
Sub-micron, metal gate, high-к dielectric, implant-free, enhancement-mode III-V mosfets
Author :
Moran, D.A.J. ; Hill, R.J.W. ; Li, X. ; Zhou, H. ; Mclntyre, D. ; Thoms, S. ; Droopad, R. ; Zurcher, P. ; Rajagopalan, K. ; Abrokwah, J. ; Passlack, M. ; Thayne, I.G.
Author_Institution :
Univ. of Glasgow, Glasgow
Abstract :
The performance of 300 nm, 500 nm and 1 mum metal gate, implant free, enhancement mode III-V MOSFETs are reported. Devices are realised using a 10 nm MBE grown Ga2O3/(GaxGd1-x)2O3 high-kappa (kappa=20) dielectric stack grown upon a delta-doped AlGaAs/InGaAs/AlGaAs/GaAs heterostructure. Enhancement mode operation is maintained across the three reported gate lengths with a reduction in threshold voltage from 0.26 V to 0.08 V as the gate dimension is reduced from 1 mum to 300 nm. An increase in transconductance is also observed with reduced gate dimension. Maximum drain current of 420 muA/mum and extrinsic transconductance of 400 muS/mum are obtained from these devices. Gate leakage current of less than 100 pA and subthreshold slope of 90 mV/decade were obtained for all gate lengths. These are believed to be the highest performance sub-micron enhancement mode III-V MOSFETs reported to date.
Keywords :
III-V semiconductors; MOSFET; aluminium compounds; gallium arsenide; gallium compounds; high-k dielectric thin films; dielectric stack; enhancement-mode III-V MOSFET; high-kappa dielectric MOSFET; implant-free MOSFET; metal gate MOSFET; sub-micron MOSFET; Councils; Dielectrics; Doping; Gallium arsenide; III-V semiconductor materials; Implants; MOSFETs; Photonic band gap; Threshold voltage; Transconductance;
Conference_Titel :
Solid State Device Research Conference, 2007. ESSDERC 2007. 37th European
Conference_Location :
Munich
Print_ISBN :
978-1-4244-1123-8
Electronic_ISBN :
1930-8876
DOI :
10.1109/ESSDERC.2007.4430979