Design of Low Voltage Tunneling-FET Logic Circuits Considering Asymmetric Conduction Characteristics

Tunnel field-effect transistor (TFET) digital circuits present the opportunity for energy efficient logic operation at low voltage due to the TFET´s steep subthreshold slope (SS) At a 400 mV supply voltage, TFET circuits have 4X higher performance than MOSFET circuits with process variation considered. Additional circuit operation effects arise because TFETs have asymmetric source-drain conduction. The N-TFET (P-TFET) has low conduction with negative (positive) V_DS bias. As shown for the first time, this asymmetric conduction can be the cause of potential circuit failures and reliability risks if not properly avoided. It is revealed that relatively large voltages can be bootstrapped within digital TFET circuits. These bootstrapped voltages are dependent on the ratio of fixed capacitance to coupling capacitance times V_DD. The bootstrapped voltages may exceed 2*V_DD, but TFET´s lower supply voltage (e.g., V) may mitigate reliability concerns. Circuit checks and redesign are proposed to avoid these problems. This bootstrapping phenomenon is unique to TFETs and may have significant speed and reliability impacts. A second, and favorable, aspect of TFET´s asymmetric source-drain conduction is that it enables compact implementations of MUX gates. Separate pull-up and pull-down networks may be shared without concern for short circuit currents only present in MOSFETs with bi-directional conduction. Circuit considerations of TFET´s asymmetric conduction are considered in detail.