A variable-size parallel regenerator for long integrated interconnections

This paper presents a low-power and low-area variant of the recently proposed parallel regeneration technique (PRT), thus providing an improved technique for the regeneration of long integrated interconnects. Taking advantage of the particular design of the regenerator in PRT, we propose a variant (called VPRT), where the regenerators along the interconnection have a variable size. Electrical simulations involving different interconnection lengths and technological processes are carried out to show that the interconnection delay, obtained with VPRT, is smaller than with PRT. A performance analysis combining area (A), delay (T), and power dissipation (P) shows that VPRT leads to an ATP metric at least 4 times better than with PRT