On synthesizing and identifying stuck-open testable CMOS combinational circuits

Author

Chakravarty, Sreejit

Author_Institution

Dept. of Comput. Sci., State Univ. of New York, Buffalo, NY, USA

fYear

1990

fDate

24-28 Jun 1990

Firstpage

736

Lastpage

739

Abstract

It is shown that a class of CMOS circuits is a testable realization and static CMOS circuits synthesized by some existing synthesis systems belong to this class. A more `direct´ solution is proposed to the problem of computing robust test-pairs for stuck-open faults by defining a new six-valued logic. This in turn gives a solution to the problem of identifying stuck-open testable circuits

Keywords

CMOS integrated circuits; combinatorial circuits; logic testing; CMOS combinational circuits; six-valued logic; stuck-open faults; stuck-open testable circuits; synthesis systems; synthesized; testable; Boolean functions; CMOS logic circuits; Circuit faults; Circuit synthesis; Circuit testing; Combinational circuits; Input variables; Logic testing; Robustness; System testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation Conference, 1990. Proceedings., 27th ACM/IEEE

Conference_Location

Orlando, FL

ISSN

0738-100X

Print_ISBN

0-89791-363-9

Type

conf

DOI

10.1109/DAC.1990.114951

Filename

114951

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2782684