A low-power and high-SFDR Direct Digital Frequency Synthesizer based on adaptive recoding CORDIC

Author

Jianfeng Zhang ; Hengzhu Liu

Author_Institution

Inst. of Microelectron. & Microprocessor, Nat. Univ. of Defense Technol., Changsha, China

fYear

2015

fDate

13-15 April 2015

Firstpage

1

Lastpage

3

Abstract

Direct Digital Frequency Synthesizer (DDS) plays an important role in communication systems. In this paper, we propose a novel DDS architecture. Compared with the conventional lookup table (LUT) based DDS, the proposed one adopts the coordinate rotation digital computer (CORDIC) algorithm to accomplish phase-to-amplitude conversion. Due to the poor accuracy of the conventional CORDIC, an adaptive recoding CORDIC is proposed. To verify the correctness and evaluate the performance, the proposed DDS is validated on a Virtex 5 FPGA development platform. Compared with a commercial implementation of DDS, the power dissipation of the proposed DDS is reduced by 21.5% at the same toggle rate. Compared to the latest CORDIC based DDS, the spurious free dynamic range (SFDR) of the proposed DDS achieves 91.67 dBc and exceeds nearly 5 dBc.

Keywords

digital arithmetic; direct digital synthesis; field programmable gate arrays; low-power electronics; CORDIC algorithm; DDS; LUT; SFDR; Virtex 5 FPGA development platform; adaptive recoding CORDIC; coordinate rotation digital computer algorithm; direct digital frequency synthesizer; lookup table; phase-to-amplitude conversion; spurious free dynamic range; Field programmable gate arrays; Inverters; Logic gates; Optimization; Random access memory; Table lookup; CORDIC; DDS; LUT; SFDR; Virtex 5 FPGA;

fLanguage

English

Publisher

ieee

Conference_Titel

Wireless and Microwave Technology Conference (WAMICON), 2015 IEEE 16th Annual

Conference_Location

Cocoa Beach, FL

Type

conf

DOI

10.1109/WAMICON.2015.7120358

Filename

7120358