27th ACM/IEEE Design Automation Conference. Proceedings 1990 (Cat. No.90CH2894-4)

The following topics are dealt with: HDL validation and intermediate format; probabilistic techniques in placement; binary decision diagrams; scheduling, mapping, and allocation techniques; timing-driven layout and verification; data management and version control; data path optimization algorithms; floorplanning; formal methods in design verification; logic synthesis and testability; layout synthesis of MOS digital cells; software engineering in design automation; Boolean methods; timing and routing optimization; layout compactors; circuit simulation; scheduling algorithms for high-level synthesis; logic simulation acceleration; data path synthesis; behavioral synthesis; performance-constrained routing; functional models for testing; decomposition and partitioning in logic synthesis; combinational test generation; and channel-oriented multilayer routing