Leakage energy reduction in register renaming

Register files are becoming a power-hungry component in future embedded microprocessors, as a lot of power reduction techniques are applied, especially on caches, which are currently the most power-hungry component. As higher performance is required for coming smart embedded systems, out-of-order execution, which requires a large number of registers, are adopted in embedded processors. In addition, deep submicron semiconductor technology leads to larger leakage current. All these situations combine to increase leakage energy consumed by registers in embedded processors. We propose a solution for this problem. By exploiting the characteristics of register renaming and the benefit from CMOS circuit techniques with sleep mode, we achieve leakage energy reduction of up to 53.6%.