Mixed mode automatic test pattern generation

The increased levels of integration of VLSI circuits is causing problems associated with testing in two main areas. First, the continual growth in circuit complexity is constantly outpacing the capabilities of current gate level Automatic Test Pattern Generators (ATPG) to produce effective test patterns economically for production testing; to overcome this problem much research work is being directed at developing test pattern generation techniques at higher levels of abstraction. Second, the reduction of basic transistor dimensions is rendering the operation of the circuits more susceptible to intermittent faults. In the past the problems of production testing and intermittent fault detection have always been considered separately. However, recent research into Concurrent Error Detection (CED) techniques for detecting intermittent faults in safety-critical VLSI circuits has also suggested that some of the hardware used to implement the CED scheme, in particular the embedded checkers, could also be used to good advantage by ATPG programs during the generation of vectors for normal production testing of circuits, thus reducing the CPU time