Hierarchical path sensitization for testability analysis and DFT

This project is aimed at making use of pre-stored testability analysis information and test vectors for integrated circuits at the cell level for generating testability analysis information and test vectors at the module level, in a hierarchical manner. This information is then used in two ways. It can be used by the functional level hierarchical test generator which is also part of the HIT methodology under development at Oxford for path planning for fault effect propagation and vector justification. This information can also be used by a system such as TIGER in planning the strategy for automatic `design for test´ insertion. The hierarchical test vector generator can also be used as a stand alone test generator. In this role it provides a more comprehensive test set when compared with the usual test vector generation algorithms, i.e. it allows a choice of test vectors for maximum fault coverage. Another feature is its ability to generate vectors which will be observable on a particular output or group of outputs of a cell. This might be used to guide the designer to make that output or group of outputs observable at the circuit level, for example by partial scan path insertion