Title :
Erratic Bit Errors in Latches
Author :
Relangi, Prasanthi ; Mitra, Subhasish
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., Stanford Univ., CA
Abstract :
Erratic bit errors are caused by erratic shifts in Vmin, the minimum supply voltage at which a design can correctly operate, due to trapping/detrapping of electrons and holes in the gate oxide. The authors study the effects of erratic bit errors in latches through SPICE simulation using the gate-to-source resistive short model. The authors demonstrate that a latch structure using a redundant latch and a C-element corrects most latch erratic bit errors and significantly reduces their impact. This structure enables chip-level power reduction by enabling chip operation at low voltage through erratic bit error correction in latches. This structure can also correct radiation-induced soft errors and is referred to as BISER or built-in-soft-error resilience structure.
Keywords :
SPICE; error statistics; flip-flops; BISER; C-element; SPICE simulation; built-in-soft-error resilience structure; erratic bit error correction; latches; radiation-induced soft errors; redundant latch; trapping/detrapping; Charge carrier processes; Clocks; Computer errors; Electron traps; Error correction; Error correction codes; Inverters; Resilience; SPICE; Voltage; BISER; Critical Resistance; Erratic bits;
Conference_Titel :
Reliability physics symposium, 2007. proceedings. 45th annual. ieee international
Conference_Location :
Phoenix, AZ
Print_ISBN :
1-4244-0919-5
Electronic_ISBN :
1-4244-0919-5
DOI :
10.1109/RELPHY.2007.369931