DocumentCode
2784008
Title
Novel Cycling-induced Program Disturb of Split Gate Flash Memory
Author
Wang, Yu-Hsiung ; Tsair, Yong-Shiuan ; Kang, An-Chi ; Chu, Wen-Ting ; Chen, Eric ; Shih, J.R. ; Chin, H.W. ; Wu, Kenneth
Author_Institution
Taiwan Semicond. Manuf. Co., Hsin-Chu
fYear
2007
fDate
15-19 April 2007
Firstpage
558
Lastpage
563
Abstract
Analytical program disturb modeling of split gate flash is presented for the first time and used to estimate post-cycling time to disturb by formulating punch through current evolution with cycling. The optimized erase voltage is chosen to achieve maximum endurance based on tradeoff of erase time pushout and post-cycling program disturb. The early punch through failure mechanism of array cycling is thus understood and eliminated by new-proposed STI corner shape
Keywords
failure analysis; flash memories; analytical program disturb modeling; cycling-induced program disturb; erase voltage; failure mechanism; split gate flash memory; Analytical models; Automotive applications; CMOS technology; Failure analysis; Flash memory; Manufacturing industries; Semiconductor device manufacture; Shape; Split gate flash memory cells; Voltage; Split gate flash; endurance; interface state; program disturb;
fLanguage
English
Publisher
ieee
Conference_Titel
Reliability physics symposium, 2007. proceedings. 45th annual. ieee international
Conference_Location
Phoenix, AZ
Print_ISBN
1-4244-0919-5
Electronic_ISBN
1-4244-0919-5
Type
conf
DOI
10.1109/RELPHY.2007.369951
Filename
4227692
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