• DocumentCode
    2784174
  • Title

    Neural Network for nanoscale architecture

  • Author

    Hé, Michel ; Klein, Jacques-Olivier ; Belhaire, Eric ; Joly, Mathilde ; Pinna, Andrea ; Garda, Patrick

  • Author_Institution
    Institut d´´Electronique Fondamentale, Université Paris Sud - CNRS, F-91405 Orsay, France
  • Volume
    1
  • fYear
    2006
  • fDate
    17-20 June 2006
  • Firstpage
    367
  • Lastpage
    370
  • Abstract
    In this paper, we investigate the use of analog neural networks to implement small logic function like Look Up Tables (LUT) in FPGA circuits (Field Programmable Gate Arrays). For that purpose, we present an architecture using tunable resistors or, alternatively, an original CNT-FET based synaptic cell. Finally, simulations demonstrate that learning using the Boltzmann machine algorithm can correct a defective circuit.
  • Keywords
    CNT-FET; Defect tolerance; Nanoscale architecture; Neural network; Circuit simulation; Field programmable analog arrays; Field programmable gate arrays; Logic functions; Machine learning; Neural networks; Programmable logic arrays; Resistors; Table lookup; Tunable circuits and devices; CNT-FET; Defect tolerance; Nanoscale architecture; Neural network;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Nanotechnology, 2006. IEEE-NANO 2006. Sixth IEEE Conference on
  • Print_ISBN
    1-4244-0077-5
  • Type

    conf

  • DOI
    10.1109/NANO.2006.247653
  • Filename
    1717103
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2784174