A hardware/software co-verification platform for ASIC design

This paper presents a hardware/software co-verification platform for ASIC design, which is based on Windows-Linux operating systems. The platform is not only used for verifying the hardware/software compatibility of maintain-and-update development ASIC chips, but also used for achieving that the hardware and software develop synchronously when developing absolutely new ASIC chips. Adopting this platform, we can not only give full functional verifications to our hardware and software more efficiently, but can also shorten the entire developmental period of our productions. In this paper, the system scheme of this platform and its operating principles are introduced, and the arithmetic of the bus-functional-model interface is illustrated. The hardware/software compatibility of several maintain-and-update chips have been guaranteed by using this platform, and the final productions´ time-to-market decreased 3 months on average.