DocumentCode :
2784302
Title :
An Investigation of External Latchup
Author :
Farbiz, Farzan ; Rosenbaum, Elyse
Author_Institution :
Dept. of Electr. & Comput. Eng., Illinois, Univ., Urbana, IL
fYear :
2007
fDate :
15-19 April 2007
Firstpage :
600
Lastpage :
601
Abstract :
Circuits are more susceptible to external latchup at elevated temperatures not only because the PNPN trigger current is lowered, but also because the minority carrier collection efficiency is increased. Collection efficiency does not scale linearly with the dimensions of the N-well. PNPN structures that are oriented perpendicular to a substrate current injector are more susceptible to latchup than are those oriented parallel
Keywords :
flip-flops; minority carriers; PNPN trigger current; external latchup; minority carrier collection efficiency; substrate current injector; Circuits; Detectors; Diodes; Electrons; Electrostatic discharge; Latches; Power supplies; Temperature distribution; Temperature sensors; Voltage;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Reliability physics symposium, 2007. proceedings. 45th annual. ieee international
Conference_Location :
Phoenix, AZ
Print_ISBN :
1-4244-0919-5
Electronic_ISBN :
1-4244-0919-5
Type :
conf
DOI :
10.1109/RELPHY.2007.369970
Filename :
4227711
Link To Document :
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