On the 6T-SRAM Cells Degradation Characterization in Ultra-Scaled CMOS Technologies

The large number of reliability challenges in stand-alone MOS transistors publications in last decades IRPS conferences put forward the difficulty to make high quality, low cost and reliable process transistor. A large work has been done at transistor level, and it is now interesting to verify experimentally the link between transistors degradation and circuit performance decrease. The 6T-SRAM cell has been chosen since its performances are directly impacted by negative bias temperature instability (NBTI) and hot carrier injection (HCI) degradation (Li, 2005)