• DocumentCode
    2784862
  • Title

    A Novel Hybrid PLL Frequency Synthesizer Using Single Electron and MOS Transistors

  • Author

    Zhang, Wancheng ; Wu, Nan-Jian

  • Author_Institution
    State Key Laboratory for Superlattices and Microstructures, Institute of Semiconductors, Chinese Academy of Sciences, P.O. Box 912, Beijing 100083, P.R. CHINA
  • Volume
    2
  • fYear
    2006
  • fDate
    17-20 June 2006
  • Firstpage
    473
  • Lastpage
    476
  • Abstract
    This paper proposes a novel hybrid phase-locked loop (PLL) using single electron transistor (SET) and metal-oxide-semiconductor (MOS) transistor. A novel hybrid voltage controlled oscillator (VCO) and hybrid logic gates using SET and MOS transistors are used to construct the hybrid PLL. The hybrid VCO has several advantages: a wide frequency tuning range, low power dissipation and large load capability. We study the performances of the hybrid PLL circuit by HSPICE simulator. Simulation results demonstrate that the hybrid circuit could well operate as a PLL at room temperature. The power dissipation of the PLL circuit is lower than 10uW.
  • Keywords
    Phase-locked loops (PLL); SPICE; Voltage controlled oscillator (VCO); hybrid; metal-oxide-semiconductor (MOS); single electron transistor (SET); Circuit optimization; Circuit simulation; Frequency synthesizers; Logic gates; MOSFETs; Phase locked loops; Power dissipation; Single electron transistors; Tuning; Voltage-controlled oscillators; Phase-locked loops (PLL); SPICE; Voltage controlled oscillator (VCO); hybrid; metal-oxide-semiconductor (MOS); single electron transistor (SET);
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Nanotechnology, 2006. IEEE-NANO 2006. Sixth IEEE Conference on
  • Print_ISBN
    1-4244-0077-5
  • Type

    conf

  • DOI
    10.1109/NANO.2006.247690
  • Filename
    1717140