Fault-Tolerant Distributed Clock Generation in VLSI Systems-on-Chip

This paper introduces a simple fault-tolerant tick generation algorithm based on Srikanth & Toueg´s consistent broadcast primitive that can be directly implemented in VLSI using asynchronous digital logic. The need for adaption originates from two peculiarities of hardware implementations: (i) Fine-grained parallel asynchronous computations, which undermines the concept of atomic steps common to all distributed computing models, and (ii) very limited resources, which makes even apparently simple operations prohibitively costly. We provide the cornerstones of the proof that the resulting algorithm is correct, and give analytic expressions for performance metrics like worst case precision and accuracy. Moreover, we outline the major building blocks of our synthesizable VHDL implementation and provide some measurement results from our FPGA prototype. Our results hence provide the required basis for investigating robust alternatives to synchronous clocking in VLSI systems-on-chip and similar applications