Simulation of Nanoscale Round-Top-Gate Bulk FinFETs with Optimal Geometry Aspect Ratio

Author

Li, Yiming ; Chen, Wei-Hsin

Author_Institution

Department of Communication Engineering, National Chiao Tung University, 1001 Ta-Hsueh Rd., Hsinchu 300, TAIWAN, ymli@faculty.nctu.edu.tw

Volume

2

fYear

2006

fDate

17-20 June 2006

Firstpage

569

Lastpage

572

Abstract

In this paper, we explore electrical characteristics of a 25 nm round-top-gate FinFET on both bulk silicon and SOI substrates. Assuming an ideal fin angle Θ = 90°, device performance of the FinFET with doped and undoped channels are simulated with a three-dimensional quantum correction transport model. Theoretical comparison shows that undoped bulk FinFETs possess promising electrical characteristics among different structures. Effect of non-ideal fin angle and fin height on device performance is investigated in terms of different short-channel effects. Optimal configuration of structure for the 25 nm round-top-gate bulk FinFETs is drawn to show the strategy of fabrication in nanoscale CMOS devices.

Keywords

CMOS; FinFETs; SOI; bulk silicon; fin angle; fin heigth; manufacturabilityt; metal gate; modeling and simulation; nanodevice; round-top; short channel effec; Computational modeling; Electric variables; FETs; Fabrication; FinFETs; Geometry; Nanoscale devices; Semiconductor device modeling; Silicon; Solid modeling; CMOS; FinFETs; SOI; bulk silicon; fin angle; fin heigth; manufacturabilityt; metal gate; modeling and simulation; nanodevice; round-top; short channel effec;

fLanguage

English

Publisher

ieee

Conference_Titel

Nanotechnology, 2006. IEEE-NANO 2006. Sixth IEEE Conference on

Print_ISBN

1-4244-0077-5

Type

conf

DOI

10.1109/NANO.2006.247716

Filename

1717166