A Reconfigurable Distributed Computing Fabric Exploiting Multilevel Parallelism

Author

Cathev, C.L. ; Bakos, Jason D. ; Buell, Duncan A.

Author_Institution

Dept. of Comput. Sci. & Eng., South Carolina Univ., Columbia, SC

fYear

2006

fDate

24-26 April 2006

Firstpage

121

Lastpage

130

Abstract

This paper presents a novel reconfigurable data flow processing architecture that promises high performance by explicitly targeting both fine- and course-grained parallelism. This architecture is based on multiple FPGAs organized in a scalable direct network that is substantially more interconnect-efficient than currently used crossbar technology. In addition, we discuss several ancillary issues and propose solutions required to support this architecture and achieve maximal performance for general-purpose applications; these include supporting IP, mapping techniques, and routing policies that enable greater flexibility for architectural evolution and code portability

Keywords

distributed processing; field programmable gate arrays; parallel architectures; reconfigurable architectures; architectural evolution; code portability; crossbar technology; data flow processing; field programmable gate arrays; multilevel parallelism; reconfigurable architecture; reconfigurable distributed computing; Computer architecture; Computer networks; Costs; Distributed computing; Fabrics; Field programmable gate arrays; Hardware design languages; Logic; Microprocessors; Parallel processing;

fLanguage

English

Publisher

ieee

Conference_Titel

Field-Programmable Custom Computing Machines, 2006. FCCM '06. 14th Annual IEEE Symposium on

Conference_Location

Napa, CA

Print_ISBN

0-7695-2661-6

Type

conf

DOI

10.1109/FCCM.2006.15

Filename

4020901