An Optimized Finite Difference Computing Engine on FPGAs

Time domain or frequency domain Finite Difference (FD) methods are one of the most popular numerical modelling techniques in the solution of scientific and engineering problems. However, these simulations are still time-consuming and cannot be used routinely except in institutes that can afford the high cost of running and maintaining supercomputers or large PC-cluster systems. In this paper, we present an efficient implementation of FPGA-based FD computing engine using acoustic wave modeling problems as an example. Instead of following the formal high-order FD expressions with standard IEEE-754 compliant floating-point multipliers and adders, we propose a new class of optimized FD schemes, whose FD coefficients are optimized to be only a few binary bits so that much fewer Logic Cell (LC) resources or on-chip multipliers are needed without deteriorating numerical accuracy criterions. Furthermore, we simplify the implementation of following floatingpoint summations by group-alignment technology. A floating-point/fixed-point hybrid accumulator with similar relative and absolute rounding errors now replaces the conventional costly floating-point adder tree.