Technology Mapping for Field Programmable Gate Arrays using Content-Addressable Memory (CAM)

This paper describes LURU, a methodology for FPGA combinational technology mapping through the parallel search capability of content-addressable memory (CAM). An overview was shown. First, a circuit is partitioned into a set of subcircuits. Topologies of these subcircuits are described using textual string representations. A precomputed set of strings for the circuit topologies that can be contained in a LUT of K or fewer inputs can be matched against the circuit representation in parallel using the CAM . By using CAM, the search space is increased over traditional technology mapping algorithms. A final mapping is produced for an FPGA device consisting of a heterogeneous network of LUT´s of K or fewer inputs