Design and FPGA implementation of digit-serial FIR filters

The design of a digit-serial N-tap FIR filter with programmable coefficients is presented. The design considers the general case of a W-bit sample word and an M-bit coefficient word. The processing of the data within the filter takes place with full precision. The output data is truncated to W bits. The design introduces a new digit-serial multiplier that guarantees minimum processing time and reduces the hardware requirements. Sign-amplitude representation for the coefficients and two´s complement for the input samples simplifies the circuit configuration and allows the use of one common two´s complement circuit for all the filter section. A 100-tap, 8-bit word length version filter is implemented using an Altera FPGA device. The filter can be used in real-time processing with sample rate range from 7.5 to 22 MHz