Design of the Multi-encrypted Circuit Based on FPGA

Author

Chai, Minggang ; Chen, Min ; Hai, Xia

Author_Institution

Key Lab. of Nondestructive Testing (Minist. of Educ.), Nanchang Hangkong Univ., Nanchang, China

Volume

4

fYear

2011

fDate

24-25 Sept. 2011

Firstpage

295

Lastpage

298

Abstract

In this paper, a FPGA-based design method of the multi-encrypted and layer-granted circuit has been proposed, overcoming program fleeting and worse reliability based on MCU. Three-encryption circuit with four bits password of each stage was described in VHDL language on Quartus II. And the method was also proposed of expanding number of password bits. The circuit has been realized on the EP1C3T144C8 chip of Altera´s FPGA which is low cost. The system could be upgraded and improved effectively by using the in-system programmable (ISP) speciality of FPGA. The experiment result shows that the circuit has the functions of multi-encrypted, arbitrary bits password and password error alarm. And the safe reliability of the system can be effectively improved.

Keywords

field programmable gate arrays; hardware description languages; logic design; microcontrollers; EP1C3T144C8 chip of Altera FPGA; FPGA-based design method; ISP; MCU; Quartus II; VHDL language; in-system programmable; layer-granted circuit; multiencrypted circuit design; password error alarm; program fleeting; reliability; three-encryption circuit; Computer architecture; Design automation; Field programmable gate arrays; Integrated circuit reliability; Light emitting diodes; Logic gates; FPGA; VHDL; arbitrary bits password; in-system programmable; multi-encrypted circuit;

fLanguage

English

Publisher

ieee

Conference_Titel

Information Technology, Computer Engineering and Management Sciences (ICM), 2011 International Conference on

Conference_Location

Nanjing, Jiangsu

Print_ISBN

978-1-4577-1419-1

Type

conf

DOI

10.1109/ICM.2011.54

Filename

6113752