Title :
Switch Box Architectures for Three-Dimensional FPGAs
Author :
Gayasen, Aman ; Vijaykrishnan, N. ; Kandemir, Mahmut ; Rahman, Arif
Author_Institution :
Dept. of Comput. Sci. & Eng., Pennsylvania State Univ.
Abstract :
In this paper, the authors explore six 3D switch box (SB) topologies for the case when the vias are fewer than the horizontal wires. Using detailed area and delay models, we estimate their impact on FPGA area, delay, and area-delay product. The results indicate that the area-delay product (ADP) depends heavily on the SB topology: our best SB reduces ADP by 9% compared to the subset SB
Keywords :
field programmable gate arrays; logic design; network topology; 3D FPGA; 3D switch box topologies; FPGA area; FPGA area-delay product; FPGA delay; SB topologies; switch box architectures; Computer architecture; Computer science; Delay estimation; Fabrics; Field programmable gate arrays; Power engineering and energy; Routing; Switches; Topology; Wires;
Conference_Titel :
Field-Programmable Custom Computing Machines, 2006. FCCM '06. 14th Annual IEEE Symposium on
Conference_Location :
Napa, CA
Print_ISBN :
0-7695-2661-6
DOI :
10.1109/FCCM.2006.66
