DocumentCode
2786715
Title
Hardware/Software Co-Design Architecture for Lattice Decoding Algorithms
Author
Liang, Cao ; Ma, Jing ; Huang, Xinming
Author_Institution
Dept. of Electr. Eng., New Orleans Univ., LA
fYear
2006
fDate
24-26 April 2006
Firstpage
339
Lastpage
340
Abstract
This paper presents hardware/software co-design architecture targeted on a single FPGA for two typical lattice decoding algorithms in MIMO system. Two levels of parallelisms are analyzed for an efficient implementation with the preprocessing part on embedded MicroBlaze soft processor and the decoder part on customized hardware. The system prototypes of the AV and VB decoders show that they support up to 34.2 Mbps and 3.15 Mbps data rate respectively on XUP Virtex-II pro developing board, which are 19 and 16 times faster than their respective implementations on a DSP
Keywords
MIMO systems; field programmable gate arrays; hardware-software codesign; lattice theory; logic design; maximum likelihood decoding; AV decoders; FPGA; MIMO system; MicroBlaze soft processor; VB decoders; hardware/software co-design architecture; lattice decoding; Computer architecture; Decoding; Digital signal processing; Field programmable gate arrays; Hardware; Lattices; MIMO; Prototypes; Software algorithms; Software prototyping;
fLanguage
English
Publisher
ieee
Conference_Titel
Field-Programmable Custom Computing Machines, 2006. FCCM '06. 14th Annual IEEE Symposium on
Conference_Location
Napa, CA
Print_ISBN
0-7695-2661-6
Type
conf
DOI
10.1109/FCCM.2006.47
Filename
4020949
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