Open Source High Performance Floating-Point Modules

Author

Hemmert, K. Scott ; Underwood, Keith D.

Author_Institution

Sandia Nat. Labs., Livermore, CA

fYear

2006

fDate

24-26 April 2006

Firstpage

349

Lastpage

350

Abstract

Given the logic density of modern FPGAs, it is feasible to use FPGAs for floating-point applications. However, it is important that any floating-point units that are used be highly optimized. This paper introduces an open source library of highly optimized floating-point units for Xilinx FPGAs. The units are fully IEEE compliant and acheive approximately 230 MHz operation frequency for double-precision add and multiply in a Xilinx Virtex-2-Pro FPGA (-7 speed grade). This speed is acheived with a 10 stage adder pipeline and a 12 stage multiplier pipeline. The area requirement is 571 slices for the adder and 905 slices for the multiplier

Keywords

IEEE standards; adders; field programmable gate arrays; floating point arithmetic; multiplying circuits; pipeline arithmetic; Xilinx Virtex-2-Pro FPGA; adder pipeline; floating-point modules; multiplier pipeline; open source library; Clocks; Delay; Field programmable gate arrays; Frequency; H infinity control; Kernel; Laboratories; Libraries; Logic; Pipeline processing; FPGA; IEEE floating point; reconfigurable computing;

fLanguage

English

Publisher

ieee

Conference_Titel

Field-Programmable Custom Computing Machines, 2006. FCCM '06. 14th Annual IEEE Symposium on

Conference_Location

Napa, CA

Print_ISBN

0-7695-2661-6

Type

conf

DOI

10.1109/FCCM.2006.54

Filename

4020954