A Reconfigurable Cluster-on-Chip Architecture with MPI Communication Layer

Author

Williams, J.A. ; Syed, I. ; Wu, J. ; Bergmann, N.W.

Author_Institution

Sch. of Inf. Technol. & Electr. Eng., Queensland Univ., Brisbane, Qld.

fYear

2006

fDate

24-26 April 2006

Firstpage

350

Lastpage

352

Abstract

In this paper, the authors present a reconfigurable cluster-on-chip architecture and supporting parallel programming software library based on the well-known message passing interface (MPI) standard. The intent is to allow designers to program multi-core reconfigurable systems on chip using the same or similar methodologies that yielded tremendous productivity improvements in the workstation and HPC cluster community. Additionally the architecture is designed to support native hardware processing modules to participate in the MPI network as fully-fledged peers

Keywords

application program interfaces; message passing; parallel programming; reconfigurable architectures; software libraries; system-on-chip; MPI communication layer; MPI standard; hardware processing modules; message passing interface standard; multicore reconfigurable; parallel programming software library; reconfigurable cluster-on-chip architecture; systems on chip; Application software; Clocks; Computer architecture; Field programmable gate arrays; Hardware; Message passing; Productivity; Software libraries; Software standards; System-on-a-chip;

fLanguage

English

Publisher

ieee

Conference_Titel

Field-Programmable Custom Computing Machines, 2006. FCCM '06. 14th Annual IEEE Symposium on

Conference_Location

Napa, CA

Print_ISBN

0-7695-2661-6

Type

conf

DOI

10.1109/FCCM.2006.14

Filename

4020955