SRC-based Cache Coherence Protocol in Chip Multiprocessor

How to improve the scalability of snooping protocol and reduce the memory access latency of directory-based protocol are critical problems for performance optimization of multiprocessor systems. In this paper, we present an SRC (sharing relation cache)-based protocol for chip multiprocessor architecture, in which protocol SRC is used to cache recently appeared sharing relations in case reuse in the near future. A two-phase write scheme is introduced to allow SRC-based protocol applicable not only in in-order network but also out-order network topology. By making full use of the temporal locality of sharing relations among processors, SRC-based protocol can heavily reduce the message traffic in CMP cache coherence protocols compared with snooping protocol. At the same time, SRC-based protocol has better memory access latency than directory-based protocol