• DocumentCode
    2787597
  • Title

    Reconfigurable mobile stream processor for ray tracing

  • Author

    Kim, Hong-Yun ; Kim, Young-Jun ; Kim, Lee-Sup

  • Author_Institution
    Dept. of EECS, Korea Adv. Inst. of Sci. & Technol. (KAIST), Daejeon, South Korea
  • fYear
    2010
  • fDate
    19-22 Sept. 2010
  • Firstpage
    1
  • Lastpage
    4
  • Abstract
    This paper presents a reconfigurable mobile stream processor for ray tracing. The processor is implemented with 16mm2 area in 0.13μm CMOS technology. The processor adopts a single instruction, multiple thread (SIMT) architecture in order to exploits instruction-level and thread-level parallelism. The SIMT architecture consists of 12 stream processors (SPs). A low hardware utilization caused by a branch divergence in SIMT architecture is addressed by reconfiguring the SPs between scalar SIMT and vector SIMT with negligible hardware overheads. A slim special function unit (SFU) with a table loader reduces the SFU area and look-up table access counts. Reusing previous result for a ray generator reduces its operations by up to 71.9%. The proposed processor achieves a peak performance of 673K rays per second while consuming 156mW.
  • Keywords
    CMOS integrated circuits; microprocessor chips; multi-threading; ray tracing; CMOS technology; SFU; instruction-level parallelism; power 156 mW; ray tracing; reconfigurable mobile stream processor; scalar SIMT; single instruction multiple thread architecture; size 0.13 micron; slim special function unit; thread-level parallelism; vector SIMT; Computer architecture; Generators; Hardware; Kernel; Parallel processing; Radio frequency; Ray tracing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Custom Integrated Circuits Conference (CICC), 2010 IEEE
  • Conference_Location
    San Jose, CA
  • ISSN
    0886-5930
  • Print_ISBN
    978-1-4244-5758-8
  • Type

    conf

  • DOI
    10.1109/CICC.2010.5617395
  • Filename
    5617395