Title :
A stacked 6.5-GHz 29.6-dBm power amplifier in standard 65-nm CMOS
Author :
Fathi, Maryam ; Su, David K. ; Wooley, Bruce A.
Author_Institution :
Stanford Univ., Stanford, CA, USA
Abstract :
A stacked amplifier architecture has been used to achieve high RF output power levels in sub-100nm CMOS. The stacking makes it possible to both operate the power amplifier (PA) from a large supply voltage and implement RF power combining. As a proof of concept, a 6.5-GHz PA has been integrated in a 65-nm standard CMOS technology. The amplifier achieves 27.4-dBm output power with an efficiency of 19.2% at 6.5 GHz when driven from a 3.6-V supply voltage and 29.6-dBm output power with an efficiency of 20.3%, when driven from a 4.6-V supply voltage.
Keywords :
CMOS analogue integrated circuits; power amplifiers; radiofrequency integrated circuits; CMOS technology; RF power combining; frequency 6.5 GHz; high RF output power; power amplifier; size 100 nm; size 65 nm; stacked amplifier architecture; voltage 3.6 V; voltage 4.6 V; CMOS integrated circuits; Capacitance; Impedance; Power amplifiers; Power generation; Radio frequency; Transistors;
Conference_Titel :
Custom Integrated Circuits Conference (CICC), 2010 IEEE
Conference_Location :
San Jose, CA
Print_ISBN :
978-1-4244-5758-8
DOI :
10.1109/CICC.2010.5617403
