DocumentCode
2787753
Title
Improving Last-Level Cache Performance by Exploiting the Concept of MRU-Tour
Author
Valero, Alejandro ; Sahuquillo, Julio ; Petit, Salvador ; López, Pedro ; Duato, José
Author_Institution
Dept. of Comput. Eng., Univ. Politec. de Valencia, Valencia, Spain
fYear
2011
fDate
10-14 Oct. 2011
Firstpage
214
Lastpage
214
Abstract
Last-Level Caches (LLCs) implement the LRU algorithm to exploit temporal locality, but its performance is quite far of Belady´s optimal algorithm as the number of ways increases. One of the main reasons because of LRU does not reach good performance in LLCs is that this policy forces a block to descend until the bottom of the stack before eviction. Nevertheless, most of the blocks that leave the MRU position are not referenced again before eviction. This work pursues to select candidate blocks to be victimized before reaching the bottom of the stack. To this end, this work defines the number of MRU-Tours (MRUTs) of a block as the number of times that a block enters in the MRU position during its live time. Based on the fact that most of the blocks exhibit a single MRUT, this work presents the family of MRUT-based algorithms aimed at exploiting this block behavior to improve performance.
Keywords
cache storage; performance evaluation; Belady optimal algorithm; LRU algorithm; MRU-tour; last-level cache performance; Benchmark testing; Complexity theory; Computers; Hardware; Parallel architectures; Last-Level Cache; MRU-Tour; replacement algorithm;
fLanguage
English
Publisher
ieee
Conference_Titel
Parallel Architectures and Compilation Techniques (PACT), 2011 International Conference on
Conference_Location
Galveston, TX
ISSN
1089-795X
Print_ISBN
978-1-4577-1794-9
Type
conf
DOI
10.1109/PACT.2011.47
Filename
6113824
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