A 550µW 10b 40MS/s SAR ADC with multistep addition-only digital error correction

Author

Cho, Sang-Hyun ; Lee, Chang-Kyo ; Kwon, Jong-Kee ; Ryu, Seung-Tak

Author_Institution

KAIST, Daejeon, South Korea

fYear

2010

fDate

19-22 Sept. 2010

Firstpage

1

Lastpage

4

Abstract

A speed-enhanced 10b asynchronous SAR ADC with multistep addition-only digital error correction (ADEC) is presented in this paper. Three virtually divided sub-DACs have a 0.5 LSB over-range between stages owing to additional decision phases incorporating DAC rearrange only. These redundancies make it possible to guarantee 10b linearity with a 37% speed enhancement under a 4b-accurate DAC settling condition at MSB decision. A prototype ADC was implemented in CMOS 0.13μm technology. The chip consumes 550μW and achieves a 50.6dB SNDR at 40MS/s under a 1.2V supply. The figure-of-merit (FOM) is 42fJ/conv-step.

Keywords

CMOS integrated circuits; analogue-digital conversion; digital-analogue conversion; CMOS technology; DAC; SAR ADC; analogue-digital conversion; digital-analogue conversion; figure-of-merit; power 550 muW; voltage 1.2 V; CMOS integrated circuits; Capacitors; Error correction; Prototypes; Redundancy; Solid state circuits; Switches; SAR ADC; digital error correction;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference (CICC), 2010 IEEE

Conference_Location

San Jose, CA

ISSN

0886-5930

Print_ISBN

978-1-4244-5758-8

Type

conf

DOI

10.1109/CICC.2010.5617408

Filename

5617408