An offset phase-locked loop spread spectrum clock generator for SATA III

A spread spectrum clock generator (SSCG) based on an offset phase-locked loop (OPLL) for the Serial AT Attachment 3 (SATA-III) is presented in this paper. The SSCG can be applied to many systems due to its characteristic of spreading the energy of frequency harmonics and reducing the radiated power per unit bandwidth. In the proposed architecture, a low-frequency spread spectrum signal is synthesized by a direct digital frequency synthesizer (DDFS) and mixed with a high frequency signal to produce a higher modulated reference source. The OPLL is employed to lock its output with the modulated reference to generate the desired spread spectrum clock. This SSCG is fabricated in a 0.13-μm CMOS technology and its area is 0.7 × 0.45 mm². It reduces main tone power by 16dB while drawing 21.16 mW from a 1.2 V supply.