Title :
An energy-efficient ring-oscillator digital PLL
Author :
Crossley, John ; Naviasky, Eric ; Alon, Elad
Author_Institution :
Univ. of California, Berkeley, CA, USA
Abstract :
A linear but fully digital phase control path and a bang-bang frequency control path enable an energy-efficient digital ring-oscillator PLL architecture. A 65nm CMOS prototype occupies 150μm × 170μm of area and generates a 3GHz clock from a 300MHz reference with 1.13ps rms period jitter while consuming 2mW from a single 1V power supply.
Keywords :
CMOS digital integrated circuits; bang-bang control; digital phase locked loops; frequency control; phase control; CMOS prototype; bang-bang frequency control path; digital phase control path; energy-efficient ring-oscillator digital PLL; frequency 3 GHz; frequency 300 MHz; power 2 mW; size 65 nm; time 1.13 ps; voltage 1 V; Bandwidth; Jitter; Noise; Phase control; Phase locked loops; Tuning;
Conference_Titel :
Custom Integrated Circuits Conference (CICC), 2010 IEEE
Conference_Location :
San Jose, CA
Print_ISBN :
978-1-4244-5758-8
DOI :
10.1109/CICC.2010.5617417
