DocumentCode :
2788528
Title :
Keynote address: critical issues in wafer scale design
Author :
Raffel, Jack I.
Author_Institution :
MIT Lincoln Lab., MA, USA
fYear :
1992
fDate :
22-24 Jan 1992
Firstpage :
1
Abstract :
Summary form only given. The author discusses critical barriers to the further developments of wafer-scale design technology and its successful transfer to industry. These include: 1) difficulty in obtaining multireticle stepper lithography for sub 2-micron fabrication, (2) limitation to two levels of metal and resulting problems in power and clock distribution, (3) excessive turnaround time because of limitations of wafer-scale design tools, and (4) compromise in performance because of the emphasis on using foundry fabrication which excludes the use of vertical links, overglass optimized for laser penetration and other custom fabrication techniques
Keywords :
VLSI; clock distribution; compromise in performance; critical barriers; critical issues; custom fabrication techniques; foundry fabrication; laser penetration; limitations; metallisation; multireticle stepper lithography; overglass; power distribution; sub 2-micron fabrication; transfer to industry; turnaround time; two levels of metal; vertical links; wafer scale design; wafer-scale design tools;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Wafer Scale Integration, 1992. Proceedings., [4th] International Conference on
Conference_Location :
San Francisco, CA
Print_ISBN :
0-8186-2482-5
Type :
conf
DOI :
10.1109/ICWSI.1992.171788
Filename :
171788
Link To Document :
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