A 10 bit piecewise linear cascade interpolation dac with loop gain ratio control

Author

Lee, Sungwoo ; Kim, Kiduk ; Park, Kyusung ; Park, Changbyung ; Lee, Byunghun ; Jeon, Jinyong ; Jung, Seungchul ; Huh, Jin ; Yang, Junhyeok ; Kim, Hyunsik ; Cho, Gyu-Hyeong

Author_Institution

KAIST, Daejeon, South Korea

fYear

2010

fDate

19-22 Sept. 2010

Firstpage

1

Lastpage

4

Abstract

This paper proposes a 10 bit linear interpolation digital-to-analog converter (DAC) with area efficiency and a high resolution for an AMLCD drive. Because this proposed structure implements a 1 bit interpolation circuit with a control block for a loop gain ratio, it shows a wide voltage range of interpolation as well as superior linearity. The proposed circuit is fabricated with Samsung 90nm CMOS 1.5V/5V technology. The power dissipation is 7uW/channel, and the chip area of the 10 bit piecewise linear DAC is only 91% of the area of a conventional 8 bit resistor DAC. The INL and DNL properties are +0.8LSB/-0.2LSB and +0.23LSB/-0.23LSB, respectively. The maximum interchannel DVO is 10mV without the application of any offset cancellation techniques.

Keywords

CMOS integrated circuits; cascade networks; digital-analogue conversion; interpolation; piecewise linear techniques; AMLCD drive; CMOS technology; DNL property; INL property; area efficiency; control block; digital-to-analog converter; interpolation circuit; loop gain ratio control; piecewise linear cascade interpolation DAC; power dissipation; size 90 nm; voltage 1.5 V; voltage 5 V; word length 10 bit; word length 8 bit; Driver circuits; Gain control; Integrated circuits; Interpolation; Transconductance; Voltage control; Voltage measurement;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference (CICC), 2010 IEEE

Conference_Location

San Jose, CA

ISSN

0886-5930

Print_ISBN

978-1-4244-5758-8

Type

conf

DOI

10.1109/CICC.2010.5617456

Filename

5617456