Title :
WSI architecture of FFT
Author :
Horiguchi, S. ; Zhang, X.X.
Author_Institution :
Dept. of Inf. Sci., Tohoku Univ., Sendai, Japan
Abstract :
The authors propose a parallel FFT (fast Fourier transform) architecture based on an N-point FFT decomposition. Performance evaluation is performed with respect to the total area of the architecture. It is clear that the architecture is simple and the execution time is faster than that of a single FFT chip. The authors also propose a fault tolerance interconnection for the FFT butterfly network by considering the complexity of the number of primitive cells
Keywords :
CMOS integrated circuits; VLSI; digital signal processing chips; fast Fourier transforms; fault tolerant computing; parallel architectures; FFT butterfly network; N-point FFT decomposition; WSI architecture; chip area; execution time; fault tolerance interconnection; parallel FFT architecture; performance evaluation; wafer scale integration; CMOS technology; Computer architecture; Fast Fourier transforms; Fault tolerance; Image processing; Integrated circuit interconnections; Parallel architectures; Speech recognition; Very large scale integration; Wafer scale integration;
Conference_Titel :
Wafer Scale Integration, 1992. Proceedings., [4th] International Conference on
Conference_Location :
San Francisco, CA
Print_ISBN :
0-8186-2482-5
DOI :
10.1109/ICWSI.1992.171795
