• DocumentCode
    2788673
  • Title

    Wafer scale integration of one- and two-dimensional linear arrays

  • Author

    Zhang, Yu ; Wang, Chia-Jiu

  • Author_Institution
    Colorado Univ., Colorado Springs, CO, USA
  • fYear
    1992
  • fDate
    22-24 Jan 1992
  • Firstpage
    65
  • Lastpage
    74
  • Abstract
    Practical methods are presented for constructing one- and two-dimensional linear arrays. it is shown that, with a given probability, a square two-dimensional array can be constructed from most of the live cells on an n×n cell wafer using wires of length θ(√log n) and channels of width O(√log n). By applying recent research results in percolation theory, one- and two-dimensional arrays of live cells embedding on a wafer can also be constructed. In terms of bounds of wire lengths and channel widths, the methods introduced are better than methods reported in the literature
  • Keywords
    VLSI; cellular arrays; circuit layout CAD; WSI; channel width bound; percolation theory; square two-dimensional array; two-dimensional linear arrays; wafer scale integration; wire length bound; Assembly systems; Computational modeling; Computer architecture; High performance computing; Packaging; Springs; Upper bound; Very large scale integration; Wafer scale integration; Wire;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Wafer Scale Integration, 1992. Proceedings., [4th] International Conference on
  • Conference_Location
    San Francisco, CA
  • Print_ISBN
    0-8186-2482-5
  • Type

    conf

  • DOI
    10.1109/ICWSI.1992.171797
  • Filename
    171797