A low-supply PLL with Enhanced Cascode Compensation and a low-supply-sensitivity CCO

Multiple techniques are proposed to realize a self-contained low-supply PLL macro that can share a digital supply thereby saving one supply regulator on the board. Enhanced Cascode Compensation features fast and slow loops to regulate the supply noise without the need of a replica. A novel topology for a current controlled oscillator (CCO) improves the supply noise rejection by more than 10 dB. A built-in 0.6V bandgap avoids the need for another 1.8V supply. Implemented in a 0.18-μm CMOS process, the whole PLL consumes less than 4 mW for 800-MHz operation. The measured random jitter is less than 2 ps. These features make it ideal for SoC integration.