A 3-D WASP module for real-time signal and data processing

Author

Lea, R.M.

Author_Institution

Aspex Microsystems Ltd., Uxbridge, UK

fYear

1992

fDate

22-24 Jan 1992

Firstpage

95

Lastpage

104

Abstract

Progress to data has concentrated on the integration of 8192 processors on a single silicon wafer (viz., a 2-D WASP (Wafer Scale Integration Associative String Processor) device). The author considers the migration of the design concept to 3-D WASP wafer stacks. A 3-D WASP architecture is described and compared with its 2-D WASP predecessor. Benefits in size, weight, power, reliability, and cost are discussed, and cost-effectiveness figures-of-merit on the order of 100 tera-OPS/ft ³, 100 tera-OPS/lb, 1 giga-OPS/W, and 10 mega-OPS/$ are forecast

Keywords

VLSI; digital signal processing chips; microprocessor chips; parallel architectures; parallel machines; real-time systems; 3-D WASP architecture; 3-D WASP module; 3-D WASP wafer stacks; WSI Associative String Processor; cost-effectiveness figures-of-merit; real-time data processing; real-time signal processing; wafer scale integration; Aerospace industry; Artificial intelligence; Concurrent computing; Costs; Data processing; Electromagnetic radiation; Fault tolerance; Radar signal processing; Radar tracking; Signal processing;

fLanguage

English

Publisher

ieee

Conference_Titel

Wafer Scale Integration, 1992. Proceedings., [4th] International Conference on

Conference_Location

San Francisco, CA

Print_ISBN

0-8186-2482-5

Type

conf

DOI

10.1109/ICWSI.1992.171800

Filename

171800