Title :
The application of yield modelling to the WASP parallel processing architecture
Author :
Sheridan, N.G. ; Bolouri, H. ; Lea, R.M.
Author_Institution :
Brunel Univ., Uxbridge, UK
Abstract :
The authors address yield modeling considerations and their impact upon the floorplanning and defect tolerance strategies of the WSI Associative String Processor (WASP) architecture. A fully parameterized, detailed yield model for the WASP architecture has been presented previously. This yield model has been developed further and applied to the various design options for future WASP devices. Using the improved model, the impact of these design options on the yield of WASP devices is assessed, leading to a set of recommendations as the optimum WASP floorplan
Keywords :
VLSI; circuit layout; microprocessor chips; parallel architectures; parallel machines; WASP; WASP devices; WASP parallel processing architecture; WSI; WSI Associative String Processor; defect tolerance strategies; design options; floorplan optimisation; floorplanning; wafer scale integration; yield model; yield modelling; Application specific processors; Chromium; Circuit faults; Computer architecture; Concurrent computing; Cost function; Parallel processing; Semiconductor device modeling; Silicon; Wafer scale integration;
Conference_Titel :
Wafer Scale Integration, 1992. Proceedings., [4th] International Conference on
Conference_Location :
San Francisco, CA
Print_ISBN :
0-8186-2482-5
DOI :
10.1109/ICWSI.1992.171802
