Title :
Design and analysis of 3D-MAPS: A many-core 3D processor with stacked memory
Author :
Healy, Michael B. ; Athikulwongse, Krit ; Goel, Rohan ; Hossain, Mohammad M. ; Kim, Dae Hyun ; Young-Joon Lee ; Lewis, Dean L. ; Lin, Tzu-Wei ; Liu, Chang ; Jung, Moongon ; Ouellette, Brian ; Pathak, Mohit ; Sane, Hemant ; Shen, Guanhao ; Woo, Dong Hyuk ;
Author_Institution :
Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA
Abstract :
We describe the design and analysis of 3D-MAPS, a 64-core 3D-stacked memory-on-processor running at 277 MHz with 63 GB/s memory bandwidth, sent for fabrication using Tezzaron´s 3D stacking technology. We also describe the design flow used to implement it using industrial 2D tools and custom add-ons to handle 3D specifics.
Keywords :
electronic engineering computing; integrated memory circuits; microprocessor chips; 3D-MAPS; 3D-stacked memory-on-processor; Tezzaron 3D stacking technology; frequency 277 MHz; many-core 3D processor; Bandwidth; Clocks; Layout; Routing; Three dimensional displays; Tiles; Timing;
Conference_Titel :
Custom Integrated Circuits Conference (CICC), 2010 IEEE
Conference_Location :
San Jose, CA
Print_ISBN :
978-1-4244-5758-8
DOI :
10.1109/CICC.2010.5617464
