Title :
100MHz-to–1GHz open-loop ADDLL with fast lock-time for mobile applications
Author :
Kim, Mi-Jo ; Kim, Lee-Sup
Author_Institution :
KAIST, Daejeon, South Korea
Abstract :
This paper presents a fast-lock wide-range all-digital delay locked loops (ADDLL) for mobile applications. The proposed open-loop architecture based on time-to-digital converter (TDC) has a lock time of 3~10 clock cycles. The multipath delay line is implemented to achieve high resolution in TDC. The frequency range selector is adopted for a wide-range operation. The ADDLL is implemented in a 0.18μm CMOS process and operates from 100MHz to 1GHz.
Keywords :
delay lock loops; frequency convertors; CMOS process; fast lock-time; fast-lock wide-range all-digital delay locked loops; frequency 100 MHz to 1 GHz; frequency range selector; mobile application; multipath delay line; open loop ADDLL; open loop architecture; size 0.18 mum; time-to-digital converter; Calibration; Clocks; Delay; Delay lines; Mobile communication; Phase measurement; Synchronization; TDC; fast-lock; open-loop DLL; wide-range;
Conference_Titel :
Custom Integrated Circuits Conference (CICC), 2010 IEEE
Conference_Location :
San Jose, CA
Print_ISBN :
978-1-4244-5758-8
DOI :
10.1109/CICC.2010.5617471
