Reconfiguration of two-dimensional VLSI arrays by time-redundancy

The authors present various approaches for reconfiguring two-dimensional VLSI arrays using pure time-redundancy, i.e., no spare cells are employed. This technique is based on the full processing utilization of fault free cells. The basic principles of the proposed time-redundancy technique are discussed. The first approach is based on a distributed execution of the reconfiguration process. The second is based on a more complex reconfiguration procedure which accounts for an iterative execution of the first approach. These approaches have been evaluated under multiple faults in both cells and in the switches of the provided interconnection network