Hierarchical redundancy for orthogonal arrays

Hierarchical redundancy using defect-tolerant replacement circuits is proposed for increasing the yield of large-area LSIs (WSIs) with mesh-connected array structures. The defect-tolerant replacement circuits can be constructed by using direct-connection paths and distributed switches in basic k-out-of-n redundancy schemes. When the proposed redundancy configurations are applied to two-dimensional orthogonal-array WSIs (wafer-scale-integrated circuits), they reduce the number of switches not covered by any spare replacements. An estimate of defect tolerance indicates that the proposed redundancy configurations can increase the integration scale under 1-micron CMOS design about 256 times over that of general nonredundant LSIs