Interpolated VCO design for a low bandwidth, low-jitter, self-biased PLL in 45 nm CMOS

A novel self-biased PLL design incorporating a low-gain interpolated inverter-based ring oscillator VCO accomplishes several improvements for general purpose clock generation, namely lower bandwidth and lower short and medium-term accumulation jitter due to thermal noise and reference clock noise, while not sacrificing PSRR, area, and PVT insensitivity. Charge pump programmability provides an effective mechanism for bandwidth adjustments without requiring large circuit duplicates. Data collected on a high-k, metal gate 45 nm process confirms the suitability of the proposed scheme.