Title :
On self-testing of array systems
Author :
Huang, W.-K. ; Lombardi, F.
Author_Institution :
Dept. of Electr. Eng., Fudan Univ., Shanghai, China
Abstract :
A novel self-testing method which is applicable to one- and two-dimensional arrays is presented. This method is based on a criterion referred to as GI (group identical) testability. GI testability is an extension and modification of PI (partition identical) testability and it is used to simplify response verification for self-testing. It is shown that the response verifier for PI testability does not detect all faults. A novel response verifier for GI-testable arrays is proposed. The proposed approach to self-testing has been evaluated with respect to a two-dimensional WSI (wafer scale integration) array whose cell implements the inner product step for matrix multiplication in 16 bits (integer format)
Keywords :
VLSI; built-in self test; digital arithmetic; 16 bits; GI testability; array systems; group identical; inner product step; matrix multiplication; response verification; self-testing method; two-dimensional WSI; Automatic testing; Built-in self-test; Computer science; Fabrication; Fault detection; Hardware; Iterative methods; Logic arrays; Partial response channels; Wafer scale integration;
Conference_Titel :
Wafer Scale Integration, 1992. Proceedings., [4th] International Conference on
Conference_Location :
San Francisco, CA
Print_ISBN :
0-8186-2482-5
DOI :
10.1109/ICWSI.1992.171824
